1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor, and more particularly to a semiconductor device with field-shield isolation structure and a manufacturing method therefor.
2. Description of the Background Art
FIG. 82 is a sectional perspective view of a semiconductor device M90 with field-shield isolation structure in the background art of the present invention. This is an SOI (Semiconductor-On-Isolation) type semiconductor device using an SOI substrate which has a film-like semiconductor layer, i.e., an SOI layer on an insulating substrate as a semiconductor substrate in which a transistor element is provided.
In the semiconductor device M90, as shown in FIG. 82, a silicon semiconductor layer is formed as an SOI layer 3 on an insulating substrate constituted of a supporting substrate 1 and a buried oxide film 2. The SOI layer 3 includes a region where each of many NMOS transistors is formed (referred to as "NMOS region" hereinafter) and a region where each of many PMOS transistors is formed ("PMOS region" hereinafter). Plate-like field-shield (gate) electrodes 5 ("FS electrode" hereinafter) are each formed in a boundary between these element regions to electrically isolating these element regions from each other.
The FS electrodes 5 are disposed in parallel at a predetermined interval to define an active region in each element region. Each FS electrode 5 is covered with a field-shield insulating layer 4 ("FS insulating layer" hereinafter) and a gate electrode 6 is disposed on the active region, extending onto the two parallel FS insulating layers 4. A gate oxide film 10 is formed between the gate electrode 6 and the active region. The FS insulating layer 4 is made of an oxide, providing electrical isolation between the FS electrode 5 and the gate electrode 6.
A drain electrode and a source electrode (both not shown), i.e., main electrodes are connected to a source/drain layer (now shown) in the SOI layer 3 through a contact hole 7 provided in a not-shown insulating layer, and a gate interconnection (not shown) is connected to the gate electrode 6 through a contact hole 8.
The contact hole 9 connected to the body contact electrode (not shown) penetrates the FS electrode 5 to be connected to the SOI layer 3 in FIG. 82, but the contact hole 9 may be provided externally of the FS electrode 5.
In the semiconductor device M90, the FS electrode 5 is reversely biased to cut off an isolation region in the SOI layer 3, and as a result, an electrical isolation between the element regions is established. For isolation between the element regions, besides this structure, a LOCOS structure which provides an isolation by selectively oxidizing the SOI layer 3 or a mesa isolation structure which separates the element regions by selectively etching the SOI layer 3.
Formation of the LOCOS structure or the mesa isolation structure, however, needs a local oxidation or a local etching of the SOI layer 3, causing local concentration of stress in the SOI layer 3. As a result, there arises a problem in terms of reliability of device, such as generation of leak current. In contrast, formation of the field-shield isolation structure needs no local oxidation or local etching. This avoids stress concentration, suppressing leak current, to ensure relatively high reliability.
The following prior-art documents have been found by searching. Outlines thereof will be presented below. In Japanese Patent Application Laid Open Gazette 8-162523, a cap insulating film made of a silicon nitride film is provided on a shield gate electrode and instead of a side wall insulating film, a side surface of the shield gate electrode is thermally oxidized.
In Japanese Patent Application Laid Open Gazette 7-201967, a side surface of a polycrystalline silicon film is thermally oxidized to reduce the width of a field-shield electrode made of a polycrystalline silicon film.
In Japanese Patent Application Laid Open Gazette 8-31928, a shield gate oxide film, a silicon nitride film and a polycrystalline silicon film are sequentially formed.
In Japanese Patent Application Laid Open Gazette 6-302779, a shield plate electrode is formed on an ONO film.
Japanese Patent Application Laid Open Gazettes 7-283300 and 9-27600, an upper surface and a side surface of a shield electrode is covered with a nitride film.
In the background-art field-shield isolation structure, various problems are left unsolved in terms of reliability due to its structure and its manufacturing method.
Showing steps for manufacturing the field-shield isolation structure in the background art with reference to FIGS. 83 to 101, these problems will be discussed below.
First, as shown in FIG. 83, an oxide film OF1, a polysilicon layer PS1 doped with an impurity (e.g., phosphorus) and an oxide film OF2 are sequentially formed on a surface of the SOI layer 3 in the SOI substrate. The SOI layer 3 has a thickness of about 1000 .ANG., the oxide film OF1 has a thickness of about 200 .ANG., the polysilicon layer PSI has a thickness of about 500 .ANG. and the oxide film OF2 has a thickness of about 1000 .ANG..
Next, in the step of FIG. 84, a patterned resist mask R1 is formed on the oxide film OF2.
In the step of FIG. 85, with the resist mask R1 used as a mask, the oxide film OF2 and the polysilicon layer PS1 are selectively removed by anisotropic etching (dry etching), to form an FS upper oxide film 41 (the first oxide film) and an FS electrode 5.
Subsequently, in the step of FIG. 86, an oxide film OF3 is formed so as to cover the oxide film OF1, the FS upper oxide film 41 and the FS electrode 5. The oxide film OF3 has a thickness of 1500 to 2000 .ANG..
In the step of FIG. 87, the oxide film OF3 is removed by anisotropic etching (dry etching), to form a side wall oxide film 42 (the second oxide film) on side surfaces of the FS upper oxide film 41 and the FS electrode 5.
After that, in the step of FIG. 88, the oxide film OF1 is removed. The oxide film OF1 serves as a protective film for protecting the source/drain region from exposure to the plasma of the dry etching, and is removed by wet etching. Through this step, the oxide film OF1 remains only below the FS electrode 5 and the side wall oxide film 42, becoming an FS gate oxide film 43. The FS upper oxide film 41, the side wall oxide film 42 and the FS gate oxide film 43 constitute the FS insulating layer 4. Together with the oxide film OF1, the FS upper oxide film 41 and the side wall oxide film 42 are etched at the same time, to become thinner. As the FS upper oxide film 41 becomes thinner, the parasitic capacitance between the FS electrode 5 and the gate electrode 6 increases, to cause degradation of operating speed of the device and increase likelihood of short circuits between these electrodes.
In the step of FIG. 89, an oxide film OF4 which is to become the gate oxide film 10 on the surface of the SOI layer 3 by thermal oxidation. In forming the oxide film OF4, the oxygen used as an oxidant goes through the FS upper oxide film 41, the side wall oxide film 42 and the FS gate oxide film 43 to oxidize the FS electrode 5. The FS electrode 5 is a doped polysilicon layer which is easily oxidize and becomes thinner in substantial thickness by oxidation.
As the FS electrode 5 becomes thinner, its electrical resistance increases and there is a possibility of not achieving the desired performance during device operation with insufficient effect of field-shield isolation.
Further, the oxygen reaching the bottom of the FS electrode 5 oxidizes an edge portion of the FS electrode 5, and as it also oxidizes the SOI layer 3 beneath the side wall oxide film 42, an edge portion of the FS gate oxide film 43 becomes thicker and the edge portion of the FS electrode 5 is warped up. That's because an edge portion is more oxidized and a central portion is less oxidized. When the edge portion of the FS electrode 5 is warped up, the distance between the FS electrode 5 and the gate electrode 6 partially decreases, to raise the possibility of an increase of parasitic capacitance therebetween and dielectric breakdown.
Subsequently, in the step of FIG. 90, a polysilicon layer PS2 which is to become the gate electrode 6 is formed by CVD on the oxide film OF4 and the FS insulating layer 4, to have a thickness of 1000 to 1500 .ANG..
In the step of FIG. 91, the polysilicon layer PS2 is selectively removed by anisotropic etching (dry etching) to form the gate electrode 6. With the gate electrode 6 used as a mask, the oxide film OF4 is selectively removed to form the gate oxide film 10.
At this time, the FS upper oxide film 41 is partially removed by overetching and the FS upper oxide film 41 partially becomes thinner. In this state, side wall oxide films 61 are formed on both sides of the gate electrode 6 to provide a lightly doped drain layer ("LDD layer" hereinafter) in the source/drain layer. Through the steps of forming an oxide film so as to cover the gate electrode 6 and then removing it by anisotropic etching (dry etching), the side wall oxide films 61 are provided, being self-aligned, on the sides of the gate electrode 6. At this time the FS upper oxide film 41 is further removed by overetching.
A silicide-protection film 11 is formed entirely on a portion which does not require formation of a silicide layer. The silicide-protection film 11 is formed on a surface of a source/drain layer of a semiconductor element where forming the silicide layer would cause defective operation.
Through the steps of forming an oxide film entirely on the semiconductor substrate and selectively removing the oxide film by anisotropic etching (dry etching), the silicide-protection film 11 is formed so as to cover a surface of a predetermined source/drain layer, and at the same time it is formed, being self-aligned, on the side surface of the FS insulating layer 4 (on the side surfaces of the side wall oxide film 42 and the FS gate oxide film 43), as shown in FIG. 92. In forming the silicide-protection film 11, the FS upper oxide film 41 is further removed by overetching and the FS upper oxide film 41 partially becomes too much thinner.
Since the edge portion of the FS electrode 5 is warped up in the step of gate oxidation, the FS electrode 5 is partially exposed in some instances.
In this state, a silicide film 12 is formed, being self-aligned, on an upper surface of the gate electrode 6 and a surface of the not-shown source/drain layer. The silicide film 12 may be any of cobalt silicide (CoSi.sub.2), titanium silicide (TiSi.sub.2), nickel silicide (NiSi.sub.2), tungsten silicide (WSi.sub.2) or the like. Since the silicide film 12 is formed on surfaces of a polysilicon layer and a silicon layer, it is formed on the exposed surface of the FS electrode 5 as shown in FIG. 93.
The silicide film 12 formed on the exposed surface of the FS electrode 5 is easily exfoliated since the exposed surface of the FS electrode 5 is small in area and it is formed where the FS upper oxide film 41 is not completely removed. If the exfoliated silicide film 12 comes into conductive dust, and remains on the semiconductor device, the remainder ill affects the operation characteristics of the semiconductor device and deteriorates production yield of the device. Moreover, if the FS electrode 5 is partially lost together with the exfoliated silicide film 12, that causes a break in the FS electrode 5 resulting in lower production yield of the device.
In the above process for manufacturing the semiconductor device, only the oxide film OF3 is removed by anisotropic etching (dry etching), to form the side wall oxide film 42 through the step of FIG. 87, and the oxide film OF1 is removed by wet etching (see FIG. 88). The oxide films OF3 and OF1, however, may be removed by dry etching at the same time, though this causes the following problem.
In the step subsequent to that of FIG. 86, the oxide films OF3 and OF1 are removed to form the side wall oxide film 42, and the oxide film OF1 is left only beneath the side wall oxide film 42, becoming the FS gate oxide film 43. In this case, as shown if FIG. 94, there is a possibility of removing the surface of the SOI layer 3 by overetching.
In particular, an edge portion of the side wall oxide film 42 is more removed than any other portions, to be partially scooped out in the SOI layer 3. One of the factors that cause this phenomenon is inconsistent density of an etchant. Thus, a dent portion DP is created in the surface of the SOI layer 3 near the edge portion of the side wall oxide film 42 as shown in FIG. 94.
After the step of forming the side wall film 42, a natural oxide film formed on the surface of the SOI layer 3 must be removed by wet etching prior to forming the gate oxide film OF3 on the surface of the SOI layer 3 as discussed with reference to FIG. 89. At this time, together with the natural oxide film, the FS upper oxide film 41 and the side wall oxide film 42 are slightly removed. This state is shown in FIG. 95.
In this figure, the broken line indicates where the FS insulating film 4 was formed before removing the natural oxide film. As is clear from FIG. 95, an edge portion EP is created in the periphery of the side wall oxide film 42 as the FS insulating film 4 is retracted.
FIG. 96 shows a state after forming the oxide film OF4 which is to become the gate oxide film. In this figure, the oxide film OF4 is formed, reflecting the shape of the edge portion EP. In other words, the edge portion EP remains in the periphery of the side wall oxide film 42. Under this condition, when the polysilicon layer PS2 which is to become the gate electrode 6 is formed, electric field concentration occurs in the edge portion EP during device operation and the electric field becomes intense, to raise strong possibility of breaking down the gate oxide film. That results in less reliability of the gate oxide film and by extension, less reliability of the MOS transistor with field-shield isolation structure.
FIGS. 98 to 100 correspond to FIGS. 91 to 93, which show the problem due to warping up of the edge portion of the FS electrode 5 which is raised also in the gate oxidation process.
Besides the above problem, there is another problem, due to the material of the FS electrode, of a short circuit between electrodes which occurs at a portion where the gate electrode of the transistor overlaps the FS electrode.
As the FS electrode 5, which is made of an N-type polysilicon doped with phosphorus (P), has large grain diameter (including crystal grain having a diameter of 0.2 to 1 .mu.m) and its oxidation is boosted along the grain boundary in the oxidation process, it is likely to be uneven.
Specifically discussing, the oxide film OF4 which is to become the gate oxide film 10 is formed on the surface of the SOI layer 3 as shown in FIG. 89, and at this time the oxygen used as an oxidant goes through the FS upper oxide film 41, the side wall oxide film 42 and the FS gate oxide film 43, to oxidize the FS electrode 5. Because of this, the FS electrode 5 becomes thinner and is warped up as discussed earlier, and at the same time the surface of the FS electrode 5 becomes uneven for the above reason.
This state is schematically shown in FIG. 101. FIG. 101 is a perspective view showing an arrangement of the FS insulating film 4, the FS electrode 5 and the gate electrode 6, for easy perception.
As the surface of the FS electrode 5 is uneven, the edge portion of the FS electrode 5 has large and small projections, as shown in FIG. 101. Therefore, electric field concentration occurs at these projections during device operation and dielectric breakdown occurs between the edge portion of the FS electrode 5 and the opposed gate electrode 6, to cause a short circuit between these electrodes.